Testing semiconductor chips requires applying test patterns to the IC chip and examining the results of the chip logic operating on those patterns. To introduce patterns to logic fed by memory elements (e.g., latches or flip-flops), scan techniques (such as Level-Sensitive Scan Design (LSSD), Boundary scan, etc.) are often used, wherein the memory elements on the chip are connected to each other in one or more scan chains, such that test patterns can be loaded in via the scan chain and applied to the logic under test. Similarly, this scan chain can be used to read out logical results of logic feeding memory elements.
Current draw and power consumption of a chip are primarily influenced by the amount of switching activity on the chip (i.e., the number of signal nets on the chip switching). During normal operation switching activity is often low (e.g., around 10% or less of the nets switching per cycle). During test, however, this activity is usually much larger due to the nature of the patterns applied. Scan test can exacerbate this situation, as a typical test pattern will not have any correlation between the data bits applied to successive memory elements in the scan chain. Thus, each memory element has a 50% probability of switching in any given scan cycle. This can be problematic, since power consumption and current draw can be limiting constraints on the ability to test a chip.
The power consumed during scan operation on average can be reduced by slowing down the rate at which scan cycles are applied. This has a negative impact onto the test time and does not solve the problem of instantaneous current variation, also known as delta-I. The delta-I problem occurs when the instantaneous switching activity is high during a specific event, and this high current is much higher than the current required by the device during the time period leading up to this high current event. This phenomena creates certain undesired effects, e.g., the power supplies in the automated test equipment (ATE) cannot respond quickly enough to the new current demand, resulting in a drop in the on-chip power supply voltage (Vdd), and the chip ground supply (Vss) moves up from a near 0 volt expected value due to the many nodes being discharged into ground during switching. Because Vdd drops and Vss increases, their difference shrinks drastically. When Vdd and Vss become too close to each other, a situation called power droop ensues, and the circuitry will begin to fail. When non-defective circuits do not function properly, the tests become invalid since both good and bad chips will fail. If the power droop is large, but not so large that the circuits begin to fail, they will operate at a much slower rate because it will generally take longer to reach the threshold voltage for a transistor to recognize a transition on its input. This again can be mitigated during scanning by simply slowing down the scan rate to allow the circuits enough time to recover from the high current spike which is seen in each scan shift cycle. However, when applying an at-speed test, one cannot afford to insert an added delay between a launch clock event and a capture clock event since that will greatly reduce the effectiveness, and even the purpose of such an at-speed test. For most at-speed scan-based tests created today, the launch clock event which stores the stimulus values for a test pattern into the memory elements is the last scan shift cycle, though it is certainly possible to use a system functional path to launch new values for an at-speed test. Although a typical test pattern has the previously mentioned attribute of approximately 50% switching during any given scan cycle, the actual scan chain elements which are set to particular values to test for a particular fault, or even for a set of faults, are typically a small fraction (less than 10%) of those on the chip. The values taken by these scan chain elements are called care bits since they are the only bits that matter when testing for their targeted faults. The remaining scan chain elements (whose values are called don't care bits) are typically loaded with random values to help in the accidental detection of non-targeted faults. Fault simulation is then used to determine which other faults have been detected by the pattern.
One method which has been used to reduce the entropy or randomness of the scan test data, and hence the switching activity during scan in of test pattern data, is to fill the don't care bits of a test pattern with repeating values based on the required care bits rather than random data (a “repeat-fill” method). The repeating values used in this context are values which result from the same scan chain input value. Thus if two memory elements are connected sequentially in a chain with no intervening inversion, the repeat-fill method will generate the same value for these two memory elements, while if two memory elements are connected sequentially in a scan chain with an intervening inversion, the repeat fill method will generate opposite values for these two memory elements. The value used to fill a sequence of don't care bits in a scan chain may be the same value (taking into account inversions) as either the preceding or following care bit in the scan chain. By using repeating values along the scan chains, the relative entropy of the scan data is greatly reduced compared with random filling, with the resulting test data being highly compressible. It has also the benefit of causing a correlation between values in consecutive memory elements in the scan chain, thus reducing switching activity when test patterns are scanned in and also when a scan cycle is used to launch new values during an at-speed test. Unfortunately, it has also the effect of reducing the number of faults detected by a given test pattern since the repeating values tend to detect fewer faults by accident compared with randomly filled scan data. This will typically result in a need for more test patterns to achieve the same fault coverage that is possible when using random-fill, resulting in longer test application times. It also does not help to reduce the switching activity when test results are scanned out, since that is a result of the functional logic operation. Switching activity during scan can also be reduced by blocking memory element outputs from propagating during scan, but this requires a more complex memory element and a blocking signal connection to the memory element (this blocking signal can be the same as a scan enable signal). It also does not reduce the switching activity when new values are launched into the combinational logic under test, nor does it reduce switching activity within the memory element itself
It is, therefore, highly desirable to have a method which reduces the switching activity during both scan in and scan out, and which, advantageously, avoids introducing detrimental effects on test pattern effectiveness and test time.
It is known that today's ICs require that during circuit placement when designing an integrated circuit semiconductor chip or module, memory elements that are connected to form scan chains are normally assigned locations on the chip based on their data input and output connections. The scan connections are typically ignored or absent during the placement process and are modified or introduced only after placement to minimize wiring costs. This is possible because the precise ordering of memory elements in a scan chain does not generally affect the chip function and, thus, any specific scan connections present before placement need not be preserved (i.e., it can be interchanged) as long as all memory elements end up in valid scan chains. Since the scan connections may still be changed after placement, there is no reason to let them influence the memory element placement, and by doing so degrade the quality of the placement result by counteracting other more important influences on the memory element placement. Clock connections to memory elements are treated in a like manner for similar reasons, but this is not germane to the present discussion.
Existing methods for ordering memory elements within scan chains following placement work minimize the amount of wiring required to implement the scan chain. Thus, preferably, the scan connections between memory elements are selected to those that are close to each other on the chip. One common scan chain ordering method uses the well-known method of simulated annealing, which makes random changes to a design, accepts all changes which improve a cost function, and also accepts changes which degrade the cost function according to a Boltzmann's probability distribution. This probability distribution is a function of a temperature parameter which is slowly reduced during the simulated annealing process, so that at the beginning of the process cost-degrading moves are more likely to be accepted, and toward the end they are very unlikely to be accepted. In the context of scan chain ordering, the random design changes include interchanging two subsections of a scan chain or of different scan chains and the cost function remains to be the total length of the scan chain. Other considerations such as the desire to balance the lengths of different scan chains may also be included the cost function. Other methods of scan chain ordering are also used, but all of them aim at reducing the scan chain length.
An example of this process is shown in FIG. 1, wherein chip 100 is shown before scan chain optimization and chip 110, after the scan chain optimization. The memory elements of the design are represented by the small squares within chip 100, and the lines interconnecting these squares represent the inter-memory element scan chain connections of an initial scan chain ordering. The actual routing of the wires which implement the scan chain connections would, in general, follow a rectilinear path, in which only vertical and horizontal wire segments are used. Thus, the interconnecting lines in chip 100 are intended to represent scan chain connectivity, and not actual wiring routes. The squares and connecting lines in chip 110 represent the memory elements of chip 100 and the inter-memory element scan chain connections, respectively, after a scan chain reordering process has been performed. It can be seen that the initial connections of chip 100 which were made without regard to the physical locations of the memory elements form a scan chain which is much longer than that formed by the optimized connections of chip 110.